correct top level entity

TopLevel.vhd

@@ -26,7 +26,7 @@ ARCHITECTURE Arch_TopLevel OF TopLevel IS
             D_OUT : OUT std_logic_vector(7 DOWNTO 0);
             d_buf_out: OUT std_logic_vector(15 DOWNTO 0)
         );
-    END Timer8254 ;
+    END COMPONENT Timer8254 ;
 
     
 BEGIN
@@ -56,4 +56,4 @@ BEGIN
     LED(9) <= MAX10_CLK1_50;
 
 
-END Arhc_TopLevel;
\ No newline at end of file
+END ARCHITECTURE;
\ No newline at end of file