Update latch_d logic equation

DialogueCPU.vhd

@@ -337,11 +337,13 @@ begin
             ))
             else '0';
 
+-- gérer la remise à 0 de latch_d_temps
+
     latch_d_temp <= '1' 
              when  ((CS='1') and(WR='1') and (RD='0') and (A0 = '1') and (D_RW=Latch))          -- if instruction is writing a control world
     else '0' when ((CS='1') and (((WR='0') and (RD='1') and (A0 = '0') and (                         -- test if instruction is a read of counter
-                            ((EtatW_q = L) and  (RW_op_q = Least))                          -- if instruction readonly lsb bytes
-                        or  ((EtatW_q = M) and ((RW_op_q = Most) or (RW_op_q = LeastMost))) -- if instruction readonly msb bytes or all bytes (and reading MSB bytes)
+                            ((EtatR_q = L) and  (RW_op_q = Least))                          -- if instruction readonly lsb bytes
+                        or  ((EtatR_q = M) and ((RW_op_q = Most) or (RW_op_q = LeastMost))) -- if instruction readonly msb bytes or all bytes (and reading MSB bytes)
                         )) 
                 or ((WR='1') and (RD='0') and (A0 = '1') and (not(D_RW=Latch)))          -- if instruction is writing a control world without latch as RW command
                 ))
@@ -352,32 +354,33 @@ begin
     RW_op <= D_RW_q when  ((CS='1') and (WR='1') and (RD='0') and (A0 = '1') and (not(D_RW=Latch))) -- if instruction is writing a control world without latch as RW command
                 else RW_op_q; -- keep the previous value of RW_op
 
-    d_buf_in_tempLSB <= D_q when ((CS='1') and (WR='1') and (RD='0') and (A0 = '0') and (EtatW_q = L))                          -- transfer of the LSB from D to d_buf_in(7 downto 0)
+    d_buf_in_tempLSB <= D when ((CS='1') and (WR='1') and (RD='0') and (A0 = '0') and (EtatW_q = L))                          -- transfer of the LSB from D to d_buf_in(7 downto 0)
         else "00000000" when ((CS='1') and (WR='1') and (RD='0') and (A0 = '0') and (EtatW_q = M) and (RW_op_q = Most))    -- if we only load the MSB force x"00" to d_buf_in(7 downto 0)
         else d_buf_inLSB_q;    -- keep the previous value of the variable
 
-    d_buf_in_tempMSB <= D_q when ((CS='1') and (WR='1') and (RD='0') and (A0 = '0') and (EtatW_q = M))                          -- transfer of the MSB from D to d_buf_in(15 downto 8)
+    d_buf_in_tempMSB <= D when ((CS='1') and (WR='1') and (RD='0') and (A0 = '0') and (EtatW_q = M))                          -- transfer of the MSB from D to d_buf_in(15 downto 8)
         else "00000000" when ((CS='1') and (WR='1') and (RD='0') and (A0 = '0') and (EtatW_q = L) and (RW_op_q = Least))    -- if we only load the MSB force x"00" to d_buf_in(15 downto 8)
         else d_buf_inMSB_q;    -- keep the previous value of the variable 
 
     -- the CPU maintain (WR='0') and (RD='1') to keep value of dbuf_out on D if the CPU prepare an other instruction dialogue CPU set D as HiZ so the CPU can write on it
-    D <= d_buf_outLSB when ((state_c=CS1) and (WR='0') and (RD='1') and (A0 = '0') and (EtatW_q = L)) -- transfer of the LSB from d_buf_out( 7 downto 0) to D 
-        else d_buf_outMSB when ((state_c=CS1) and (WR='0') and (RD='1') and (A0 = '0') and (EtatW_q = M) and (WR='0') and (RD='1')) -- transfer of the MSB from d_buf_out(15 downto 8) to D
+    D <= d_buf_outLSB when ((state_c=CS1) and (WR='0') and (RD='1') and (A0 = '0') and (EtatR_q = L)) -- transfer of the LSB from d_buf_out( 7 downto 0) to D 
+        else d_buf_outMSB when ((state_c=CS1) and (WR='0') and (RD='1') and (A0 = '0') and (EtatR_q = M)) -- transfer of the MSB from d_buf_out(15 downto 8) to D
         else "ZZZZZZZZ";    -- other instruction does not impact the bus
 
-    -- rd_q ?
+    -- rd_q ? yes so they are only update when state_c = CS1 and CS = 0 (at the end of the instruction) only input use as a condition and change in the same instruction
+    -- Pay attention to not update too early and Msb are modified wheras only LSB should have been 
     EtatW <= M when((state_c=CS1)  and (((WR_q='1') and (RD_q='0') and (A0_q = '0') and (EtatW_q = L) and (RW_op_q = LeastMost))       -- if loading in leastMost mode and EtatW_q = L
-                  or ((WR_q='1') and (RD_q='0') and (A0_q = '1') and (D_RW = Most))))   -- if writing control word D_RW and mode is leastMost or Least
+                  or ((WR_q='1') and (RD_q='0') and (A0_q = '1') and (D_RW_q = Most))))   -- if writing control word D_RW and mode is leastMost or Least
         
         else L when ((state_c=CS1) and (((WR_q='1') and (RD_q='0') and (A0_q = '0') and (EtatW_q = M) and (RW_op_q = LeastMost))       -- if loading in leastMost mode and EtatW_q = M
-                or ((WR_q='1') and (RD_q='0') and (A0_q = '1') and ((D_RW_q = LeastMost) or (D_RW = Least)))))                                -- if writing control word D_RW and mode is Most
+                or ((WR_q='1') and (RD_q='0') and (A0_q = '1') and ((D_RW_q = LeastMost) or (D_RW_q = Least)))))                                -- if writing control word D_RW and mode is Most
                 
         else EtatW_q; -- keep previous value
 
-    EtatR <= M when ((state_c=CS1) and (((WR_q='0') and (RD_q='1') and (A0_q = '0') and (EtatW_q = L) and (RW_op_q = LeastMost))       -- if reading in leastMost mode and EtatW_q = L
+    EtatR <= M when ((state_c=CS1) and (((WR_q='0') and (RD_q='1') and (A0_q = '0') and (EtatR_q = L) and (RW_op_q = LeastMost))       -- if reading in leastMost mode and EtatW_q = L
                 or ((WR_q='1') and (RD_q='0') and (A0_q = '1') and (D_RW_q = Most))))   -- if writing control word D_RW and mode is leastMost or Least
 
-        else L when ((state_c=CS1) and (((WR_q='0') and (RD_q='1') and (A0_q = '0') and (EtatW_q = M) and (RW_op_q = LeastMost))       -- if reading in leastMost mode and EtatW_q = M
+        else L when ((state_c=CS1) and (((WR_q='0') and (RD_q='1') and (A0_q = '0') and (EtatR_q = M) and (RW_op_q = LeastMost))       -- if reading in leastMost mode and EtatW_q = M
             or ((WR_q='1') and (RD_q='0') and (A0_q = '1') and ((D_RW_q = LeastMost) or (D_RW_q = Least)))))                               -- if writing control word D_RW and mode is Most
             
         else EtatR_q; -- keep previous value

Simulation/TestTimer8254.do

@@ -62,7 +62,7 @@ proc wave_cfg { } {
 #
 #>	main cmd:	add wave signal-name
 
-	#restart -nowave all
+	restart -nowave all
 	wave_cfg
 
 

Test_timer.vhd

@@ -68,10 +68,12 @@ architecture archTesTimerWithCpu of Test_timer is
     constant	PM : PAS_tab( 0 to 2**pm_w-1 ) := (
         -- first default address = 0x00
             0 => x"101C",	 1 => x"2006",	 2 => x"1030",	 5 => x"2069",
-            9 => x"102C",	 10 => x"2001",
+            6 => x"2001",
+            --9 => x"102C",	 10 => x"2001",
 
-            15 => x"101C",	16 => x"3000",--	27 => x"1805",
-            20 => x"1005",	29 => x"1960",--	30 => x"B800",	31 => x"BA62",
+            15 => x"100C",	 20 => x"3000", 22 => x"3000",
+            --	27 => x"1805",
+            --20 => x"1005",	29 => x"1960",--	30 => x"B800",	31 => x"BA62",
             --32 => x"0023",	33 => x"CD60",	34 => x"AE60",	35 => x"1BFF",
             --36 => x"7003", 	37 => x"03DC",
         -- ...