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library ieee;
library work;
use ieee.std_logic_1164.all;
use work.EtatPak.all;
entity DialogueCPU is
port (
RD, WR, A0, CS: in std_logic;
sortie : out std_logic;
D : inout std_logic_vector(7 downto 0) := "ZZZZZZZZ";
d_buf_out : in std_logic_vector(15 downto 0);
d_buf_in : out std_logic_vector(15 downto 0);
charg_d, latch_d : out std_logic
) ;
end DialogueCPU ;
architecture archDialogueCPU of DialogueCPU is
signal EtatW, EtatR : state := L;
signal ctrlWord : std_logic_vector(7 downto 0) ;
alias RW_op : std_logic_vector(1 downto 0) is ctrlWord(5 downto 4);
alias D_RW : std_logic_vector(1 downto 0) is D(5 downto 4);
alias d_buf_inMSB : std_logic_vector(7 downto 0) is d_buf_in(15 downto 8);
alias d_buf_inLSB : std_logic_vector(7 downto 0) is d_buf_in( 7 downto 0);
alias d_buf_outMSB : std_logic_vector(7 downto 0) is d_buf_out(15 downto 8);
alias d_buf_outLSB : std_logic_vector(7 downto 0) is d_buf_out( 7 downto 0);
constant Latch : std_logic_vector(1 downto 0) := "00";
constant Least : std_logic_vector(1 downto 0) := "01";
constant Most : std_logic_vector(1 downto 0) := "10";
constant LeastMost : std_logic_vector(1 downto 0) := "11";
begin
--sortie <= '0' when (WR = '1') and (RD = '0') and (A0 = '0') and ((D_RW = Least) or (D_RW = Most) or (D_RW = LeastMost)) else '1';
sortie <= '0' when (WR = '1') and (RD = '0') and ( ((A0 = '1') and ((D_RW = Least) or (D_RW = Most) or (D_RW = LeastMost))) or (A0 = '0') ) else '1';
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ReceptData : process(CS)
begin
if rising_edge(CS) then
if ((WR = '1') and (RD = '0') and (A0 = '1')) then -- Reception ctrl
D <= "ZZZZZZZZ";
charg_d <= '0';
if (D_RW = Latch) then
latch_d <= '1';
--sortie <= '1';
else
RW_op <= D_RW;
latch_d <= '0';
--sortie <= '0';
if D_RW = Most then
EtatW <= M;
EtatR <= M;
else
EtatW <= L;
EtatR <= L;
end if ;
end if ;
elsif((WR = '1') and (RD = '0') and (A0 = '0')) then -- reception data
D <= "ZZZZZZZZ";
if EtatW = L then
d_buf_inLSB <= D;
if (RW_op = LeastMost) then
EtatW <= M;
charg_d <= '0';
elsif (RW_op = Least) then
d_buf_inMSB <= x"00";
charg_d <= '1';
end if ;
elsif EtatW = M then
d_buf_inMSB <= D;
if (RW_op = LeastMost) then
EtatW <= L;
charg_d <= '1';
elsif (RW_op = Most) then
charg_d <= '1';
d_buf_inLSB <= x"00";
end if ;
else
end if ;
elsif ((WR = '0') and (RD = '1') and (A0 = '0')) then -- envoie data
charg_d <= '0';
if EtatR = L then
D <= d_buf_outLSB;
if RW_op = LeastMost then
EtatR <= M;
elsif RW_op = Most then
latch_d <= '0';
end if ;
elsif EtatR = M then
D <= d_buf_outMSB;
if RW_op = LeastMost then
EtatR <= L;
latch_d <= '0';
elsif RW_op = Most then
latch_d <= '0';
end if ;
end if ;
else
end if ;
end if ;
end process ; -- ReceptData
-- Pro_Etat_W : process
-- begin
-- end process ; -- Pro_Etat_W
-- Pro_Etat_R : process
-- begin
-- end process ; -- Pro_Etat_R
end architecture ; -- archDialogueCPU
architecture archImplantation of DialogueCPU is
signal EtatW_q, EtatR_q : state := L;
signal EtatW, EtatR : state;
signal ctrlWord : std_logic_vector(7 downto 0) ;
alias RW_op : std_logic_vector(1 downto 0) is ctrlWord(5 downto 4);
alias D_RW : std_logic_vector(1 downto 0) is D(5 downto 4);
alias d_buf_inMSB : std_logic_vector(7 downto 0) is d_buf_in(15 downto 8);
alias d_buf_inLSB : std_logic_vector(7 downto 0) is d_buf_in( 7 downto 0);
alias d_buf_outMSB : std_logic_vector(7 downto 0) is d_buf_out(15 downto 8);
alias d_buf_outLSB : std_logic_vector(7 downto 0) is d_buf_out( 7 downto 0);
constant Latch : std_logic_vector(1 downto 0) := "00";
constant Least : std_logic_vector(1 downto 0) := "01";
constant Most : std_logic_vector(1 downto 0) := "10";
constant LeastMost : std_logic_vector(1 downto 0) := "11";
constant inputVectWidth : integer := 29;
COMPONENT DFFEXb
generic(width : integer := inputVectWidth);
port (
clk : in std_logic;
Din : in std_logic_vector((width-1) downto 0) ;
Q : out std_logic_vector((width-1) downto 0)
) ;
end COMPONENT;
signal inputVect : std_logic_vector((inputVectWidth-1) downto 0) ;
alias D_q : std_logic_vector(7 downto 0) is inputVect(7 downto 0) ;
alias RD_q : std_logic is inputVect(8);
alias WR_q : std_logic is inputVect(9);
alias A0_q : std_logic is inputVect(10);
alias d_buf_q : std_logic_vector(15 downto 0) is inputVect(26 downto 11) ;
alias RW_op_q : std_logic_vector(1 downto 0) is inputVect(28 downto 27) ;
begin
inputVect <= ( RW_op & d_buf_out & A0 & WR & RD & D) ;
DFF_Etats_W_R : process( CS )
begin
if rising_edge(CS) then
EtatW_q <= EtatW_q;
EtatR_q <= EtatR_q;
end if ;
end process ; -- DFF_Etats_W_R
end archImplantation ; -- archImplantation