From fb3a65fff180907bde2bed2179972b78f3bedced Mon Sep 17 00:00:00 2001 From: "Quentin.Milot" <quentin.milot@insa-rennes.fr> Date: Mon, 5 Apr 2021 16:35:38 +0200 Subject: [PATCH] [MODIFIED] FSM Resets for working --- FSM_Reset_Compteur0.vhd | 30 +++++++++++++++++++++++++++++- FSM_Reset_Dialogue_CPU.vhd | 30 ++++++++++++++++++++++++++++-- 2 files changed, 57 insertions(+), 3 deletions(-) diff --git a/FSM_Reset_Compteur0.vhd b/FSM_Reset_Compteur0.vhd index d3100d7..0f3e33b 100644 --- a/FSM_Reset_Compteur0.vhd +++ b/FSM_Reset_Compteur0.vhd @@ -4,12 +4,40 @@ use work.EtatResetPak.all; ENTITY FSM_Reset_Compteur0 IS GENERIC (width : integer := 16); - PORT (); + PORT (R: OUT std_logic :='Z'; + Rd,clk,charge_d : IN std_logic); END FSM_Reset_Compteur0; ARCHITECTURE Arch_FSM_Reset_Compteur0 OF FSM_Reset_Compteur0 IS SIGNAL state_c : state_Res_Compt := init_Compt; +SIGNAL state_temp : state_Res_Compt :=init_Compt; + +BEGIN + + state_temp <= reset_Compt_state WHEN state_c=init_Compt AND (charge_d='1') + else init_Compt WHEN state_c=init_Compt + else init_Compt WHEN state_c=reset_Compt_state AND (Rd='0') + else reset_Compt_state WHEN state_c=reset_Compt_state AND (Rd='1') + else init_Compt; + + Attribution_etat:PROCESS (clk) + BEGIN + if(clk='1') then + state_c<=state_temp; + END IF; + END PROCESS; + + Sortie_etat:PROCESS(state_c,Rd) + BEGIN + case state_c is + WHEN init_Compt => + R<='0'; + WHEN reset_Compt_state => + R<=NOT(Rd); + WHEN Others => NULL; + END CASE; + END PROCESS; END Arch_FSM_Reset_Compteur0; \ No newline at end of file diff --git a/FSM_Reset_Dialogue_CPU.vhd b/FSM_Reset_Dialogue_CPU.vhd index 0975561..3911c18 100644 --- a/FSM_Reset_Dialogue_CPU.vhd +++ b/FSM_Reset_Dialogue_CPU.vhd @@ -3,13 +3,39 @@ USE ieee.std_logic_1164.ALL; use work.EtatResetPak.all; ENTITY FSM_Reset_Dialogue_CPU IS - GENERIC (width : integer := 16); - PORT (); + PORT (Rd: OUT std_logic :='Z'; + R,CS : IN std_logic); END FSM_Reset_Dialogue_CPU; ARCHITECTURE Arch_FSM_Reset_Dialogue_CPU OF FSM_Reset_Dialogue_CPU IS SIGNAL state_c : state_Res_Dial :=init_Dial; +SIGNAL state_temp : state_Res_Dial :=init_Dial; BEGIN + + state_temp <= reset_Dial_state WHEN state_c=init_Dial AND (R='1') + else init_Dial WHEN state_c=init_Dial + else init_Dial WHEN state_c=reset_Dial_state AND (R='0') + else reset_Dial_state WHEN state_c=reset_Dial_state AND (R='1') + else init_Dial; + + Attribution_etat:PROCESS (CS) + BEGIN + IF(CS='1') THEN + state_c<=state_temp; + END IF; + END PROCESS; + + Sortie_etat:PROCESS(state_c,R) + BEGIN + CASE state_c IS + WHEN init_Dial => NULL; + + WHEN reset_Dial_state => + Rd<=R; + WHEN Others => NULL; + END CASE; + END PROCESS; + END Arch_FSM_Reset_Dialogue_CPU; \ No newline at end of file -- GitLab