diff --git a/Test_timer.vhd b/Test_timer.vhd
index f70e4ec1ebff894711e6b3dcae0a1ec067aeadf1..dd196ced7d48ee550fd57b134c297a68ee4d57e1 100644
--- a/Test_timer.vhd
+++ b/Test_timer.vhd
@@ -56,26 +56,43 @@ architecture archTesTimerWithCpu of Test_timer is
-- 3 : read data
-- value for D bus byte[7..0]
- -- for opcode 0 not used
+ -- for opcode 0 NOP
-- for opcode 1 control world(RW_op = byte[5..4])
+ -- latch command : x"1000",
+ -- Least mode : x"1010"
+ -- Most mode : x"1020"
+ -- LeastMode mode : x"1030"
-- for opcode 2 value to load in timer
+ -- Load command : x"20 <D8b>"
-- for opcode 3 not used (D force to HiZ)
+ -- Read command : x"3000"
constant pm_w : positive := 16;
constant inst_w : positive := 16;
type PAS_tab is array(natural range <>) of std_logic_vector(inst_w-1 downto 0);
constant PM : PAS_tab( 0 to 2**pm_w-1 ) := (
- -- first default address = 0x00
- 0 => x"101C", 1 => x"2006", 2 => x"1030", 5 => x"2069",
- 6 => x"2001",
- --9 => x"102C", 10 => x"2001",
-
- 15 => x"100C", 20 => x"3000", 22 => x"3000",
- -- 27 => x"1805",
- --20 => x"1005", 29 => x"1960",-- 30 => x"B800", 31 => x"BA62",
- --32 => x"0023", 33 => x"CD60", 34 => x"AE60", 35 => x"1BFF",
- --36 => x"7003", 37 => x"03DC",
+ -- Least Mode
+ 0 => x"1010",
+ -- Load, latch
+ 1 => x"2006", 3 => x"1000",
+ -- Read, Read, Latch
+ 6 => x"3000", 8 => x"3000", 9 => x"1000",
+
+ -- LeastMost Mode
+ 11 => x"1030",
+ -- load, load
+ 12 => x"2069", 13 => x"2001",
+ -- Latch, Read, Read
+ 14 => x"1000", 15 => x"3000", 16 => x"3000",
+ -- Read, load, Read, Load
+ 19 => x"3000", 20 => x"2056", 21 => x"3000", 27 => x"203B",
+
+ -- Most Mode
+ 32 => x"1020",
+ -- load, Read, latch, Read
+ 35 => x"2005", 36 => x"3000", 37 => x"1000", 40 => x"3000",
+
-- ...
-- default value for other ROM cells
others => x"0000" -- NOP instruction